1. Field of the Invention
The present invention relates in general to printed circuit boards, and more particularly to a method and apparatus of providing a high density printed circuit substrate.
2. Description of the Related Art
Integrated circuits are typically assembled into a package that is soldered to a printed circuit board. The integrated circuit may be mounted to a substrate which has a plurality of contacts such as solder balls or pins that are soldered to the printed circuit board. The contacts are typically located on a bottom surface of the substrate while the integrated circuit is typically located on a top surface of the substrate. The package substrate may contain routing traces, power/ground planes and vias that electrically connect the integrated circuit with the contacts located on the other side of the substrate. The substrate may have multiple layers of routing traces and vias to interconnect the integrated circuit and the contacts.
FIGS. 1A-E show a conventional process for forming a substrate. As shown in FIGS. 1A and 1B, a base laminate is first formed. In FIG. 1A, a conductive layer 2 such as copper is first electroplated onto a drum 4. The surface 6 of the conductive material 2 that is adjacent to the drum 4 is typically smooth, while the surface 8 of the conductive layer 2 that is on the opposite side of the drum 4 is typically matted. In addition, the matted surface 8 of the conductive layer 2 is typically treated by adding nodules or pinning teeth to the surface 8 so as to enhance the bond strength of the conductive layer 2 to a dielectric (see FIG. 1B) during the lamination process. The surface roughness .mu. of surface 8 is typically greater than 6.0 microns (peak-to-valley, R.sub.Z DIN) as measured with a contact profilometer. A silane coupling promoter 10 is subsequently attached to the matted surface 8 to further enhance the bond strength of the conductive layer 2. As shown in FIG. 1B, the treated conductive layer 2 is then laminated onto one or both sides of a dielectric layer 12 under heat and pressure (only one layer 2 is shown as being attached to the dielectric layer 12 in FIG. 1B) to form a base laminate 14. An etch resist mask 16 may be patterned onto the base laminate 14 as shown in FIG. 1C. The resist mask 16 is then patterned, as shown in FIG. 1D, and the conductive layer 2 is subsequently etched to provide a substrate 18 as shown in FIG. 1E. The conductive layer 2 is typically 5-18 .mu.m thick. The etch resist is subsequently removed to provide the circuitized substrate as shown in FIG. 1F.
During such conventional production of printed circuit substrates, residual metal inclusions (such as copper inclusions) are typically formed because slivers of the nodules break away from the matted surface 8 of the conductive layer 2 during the lamination process. Since the etching process typically fails to remove these deeply embedded slivers, the imperfections remaining in the laminate 14 act as seed sites for electroless plating, and subsequently cause conductive defects on the laminate 14 surface. These defects result in potential shorts in the circuitry produced by the customer.
With design goals of providing increasingly higher density printed circuit boards, the trace line and space features of printed circuit boards are proportionally decreased. In addition, the diameters of pads that capture vias on the circuit boards need to be reduced. As the trace lines and space features become finer (e.g., 10-50 .mu.m), the problem of embedded slivers become more pronounced. Moreover, to etch fine lines and spaces, the conductive layer 2 (e.g., a copper layer) needs to be much thinner.
In addition, during conventional production of printed circuit boards, the substrate is typically subjected to various pressure and temperature cycles. One typical method for fabricating laminates employs a flat-bed lamination press using hydraulic pressure. Electrodeposited copper foils are laminated to thermosetting resin-cloth prepregs under heat and pressure. The resultant laminate typically has unacceptable levels of residual stresses, primarily arising from the mechanical interaction of the treated copper tooth structure and the crosslinked laminate surface. Subsequently, during etching of the first conductive layer 2 (e.g., the copper layer), the built-in stress causes very large and unpredictable dimensional movements, requiring the use of increased capture pad diameters.
Accordingly, there is a need in the technology for an apparatus and method for providing a high density printed circuit substrate with reduced conductive defects. There is also a need in the technology for an apparatus and method for providing a high density printed circuit substrate having improved dimensional consistency, so that fine line formation may be achieved, and pad size dimensions may be decreased. In addition, there is a need in the technology for providing a circuit substrate having a reduced copper thickness. There is a further need in the technology for a substrate with very smooth surfaces, which facilitates the production of printed circuit substrates having very fine lines and spaces, with significantly reduced occurrence of defects.